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hys72t32000gr (256 mbyte) hys72t64001gr (512 mbyte) HYS72T64020GR (512 mbyte) ddr2 registered dimm modules memory products never stop thinking. data sheet, v0.22,feb. 2004
infineon technologies rainer.weidlich@infineon.com 22.04 hys72t32000gr, hys72t64001gr HYS72T64020GR preliminary datasheet rev. 0.22 (2.04) low profile 240-pin registered ddr2 sdram modules datasheet 256 mbyte & 512 mbyte modules pc2-3200r /-4200r /-5300r 1.0 description the infineon hys72t32000gr, HYS72T64020GR and hys72t64001 are low profile registered dimm modules with 30,00 mm height ba sed on ddr2 technology. dimms are available in 32m x 72 (256 mbyte), 2 x 32m x 72 (512 mb yte) and 64m x 72 (512 mbyte) organisation and density, intended for mounting into 240 pin connector sockets. the memory array is designed with 256mbit double data rate (ddr2) synchronous drams for ecc applications. all control and address signals are re-driven on the dimm using register devices and a pll for the clock distribution. this reduces c apacitive loading to the system bus, but adds one cycle to the sdram timing. decoupling capacitor s are mounted on the pcb board, which provide a proper voltage supply impedance over the whol e frequency range of operations as number and values are accordant to the jedec specificati on. the dimms feature serial presence detect based on a serial e 2 prom device using the 2-pin i 2 c protocol. the first 128 bytes are programmed with configuration data and the second 128 bytes are available to the customer. ? 240-pin registered 8-byte ecc dual-in-line ddr2 sdram module for pc, workstation and server main memory applications one rank 32mb x 72, 64mb x 72 and two ranks 64mb 72 organizations jedec standard double data rate 2 synchronous drams (ddr2 sdrams) with +1.8v ( 0.1 v) power supply modules built with 256 mb ddr2 sdrams in 60-ball fbga chipsize packages programmable cas latencies (3, 4 & 5), burst length (4 & 8) and burst type. auto refresh and self refresh all inputs and outputs sstl_1.8 compatible re-drive for all input signals using register and pll devices. ocd (off-chip driver impedance adjustment) and odt (on-die termination) serial presence detect with e 2 prom low profile modules form factor: 133.35 mm x 30,00 mm (mo-237) based on jedec standard reference card designs raw card ?a?, ?b? and ?c?. performance: speed grade indicator -5 -3.7 -3 unit component speed grade on module ddr2-400 ddr2-533 ddr2-667 module speed grade pc2-3200 pc2-4200 pc2-5300 max. clock frequency @ cl = 3 200 200 200 mhz max. clock frequency@ cl = 4 & 5 200 266 333 mhz
hys72txx0xxgr registered ddr2 sdram-modules infineon technologies 3 2.04 1.1 ordering information 1.2 address format type & partnumber compliance code description sdram technology pc2-3200 (ddr2-400): hys72t32000gr-5-a pc2-3200r-33310-a one rank 256 mb reg. dimm 256 mbit (x8) HYS72T64020GR-5-a pc2-3200r-33310-b two ranks 512 mb reg. dimm 256 mbit (x8) hys72t64001gr-5-a pc2-3200r-33310-c one ranks 512 mb reg.dimm 256 mbit (x4) pc2-4200 (ddr2-533): hys72t32000gr-3.7-a pc2-4200r-44410-a one rank 256 mb reg. dimm 256 mbit (x8) HYS72T64020GR-3.7-a pc2-4200r-44410-b two ranks 512 mb reg. dimm 256 mbit (x8) hys72t64001gr-3.7-a pc2-4200r-44410-c one ranks 512 mb reg.dimm 256 mbit (x4) pc2-5300 (ddr2-667): hys72t32000gr-3-a pc2-5300r-44410-a one rank 256 mb reg. dimm 256 mbit (x8) HYS72T64020GR-3-a pc2-5300r-44410-b two ranks 512 mb reg. dimm 256 mbit (x8) hys72t64001gr-3-a pc2-5300r-44410-c one ranks 512 mb reg.dimm 256 mbit (x4) notes: 1. all part numbers end with a place code, designating the s ilicon die revision. example: hys 72t32000gr-5-a, indicating rev. a dies are used for ddr2 sdram components. for all infineon ddr2 module and component nomenclature see section 8 of this datasheet. 2. the compliance code is printed on the module label and describes the speed grade, f.e. ?pc2-4200r-44410-c?, where 4200r means registered dimm modules with 4.26 gb/sec module bandwidth and ?44410? means cas latency = 4, trcd latency = 4 and trp latency = 4 using the latest jedec spd revision 1.0 and produced on the raw card ?c?. part number dimm density organization memory ranks ddr2- sdrams # of sdrams # of row/bank/ column bits hys72t32000gr 256 mb 32mb 72 1 (256mb) 32mb 8 9 13/2/10 HYS72T64020GR 512 mb 2 x 32mb 72 2 (256mb) 32mb 8 18 13/2/10 hys72t64001gr- 512 mb 64mb x 72 1 (256mb) 64mb 4 18 13/2/11
hys72txx0xxgr registered ddr2 sdram-modules infineon technologies 4 2.04 1.3 components on modules and rawcard 1.4 pin definition and function dimm density dram components reference datasheet pll register raw card 256 mb hyb18t256800ac 1:10, 1.8v, cu877 1:1 25-bit 1.8v sstu32864 a 512 mb hyb18t256800ac 1:10, 1.8v, cu877 1:2 14-bit 1.8v sstu32864 b 512 mb hyb18t256400ac 1:10, 1.8v, cu877 1:2 14-bit 1.8v sstu32864 c for a detailed description of all functionalities of the dram components on these modules see the referenced component datasheet pin name description pin name description a[12:0] row address inputs cb[7:0] dimm ecc check bits a11, a[9:0] column address inputs 4) dqs[8:0] sdram low data strobes a10/ap column address input for auto- precharge dm[8:0] / dqs[17:9] sdram low data mask/ high data strobes ba[1:0] sdram bank selects dqs [17:0] sdram differential data strobes ck0 clock input (positive line of differential pair) scl serial bus clock ck0 clock input (negative line of differential pair) sda serial bus data line ras row address strobe sa[2:0] slave address select cas column address strobe v dd power (+ 1.8 v) we read/write input v ref i/o reference supply cs [1:0] chip selects 3) v ss ground cke[1:0] clock enable 3) v ddspd eeprom power supply odt[1:0] active termination control lines 1) 3) reset register and pll control pin 2) dq[63:0] data input/output nc no connection 1) active termination only applies to dq, dqs, dqs and dm signals 2) when low, all register outputs will be dr iven low and the pll clocks to the dram and registers will be set to low levels (th e pll will remain synchronized with the input clock 3) cs1 , odt1 and cke1 are used on dual rank modules only 4) column address a11 is used on modules based on x4 organised 256mb ddr2 components only.
hys72txx0xxgr registered ddr2 sdram-modules infineon technologies 5 2.04 1.5 pin configuration pin# symbol pin# symbol pin# symbol pin# symbol 1 vref 121 vss 61 a4 181 vddq 2 vss 122 dq4 62 vddq 182 a3 3 dq0 123 dq5 63 a2 183 a1 4 dq1 124 vss 64 vdd 184 vdd 5 vss 125 dm0, dqs9 key key 6dqs0 126 dqs9 65 vss 185 ck0 7 dqs0 127 vss 66 vss 186 ck0 8 vss 128 dq6 67 vdd 187 vdd 9 dq2 129 dq7 68 nc 188 a0 10 dq3 130 vss 69 vdd 189 vdd 11 vss 131 dq12 70 a10/ap 190 ba1 12 dq8 132 dq13 71 ba0 191 vddq 13 dq9 133 vss 72 vddq 192 ras 14 vss 134 dm1, dqs10 73 we 193 cs0 15 dqs1 135 dqs10 74 cas 194 vddq 16 dqs1 136 vss 75 vddq 195 odt0 17 vss 137 nc 76 cs1 196 nc 18 reset 138 nc 77 odt1 197 vdd 19 nc 139 vss 78 vddq 198 vss 20 vss 140 dq14 79 vss 199 dq36 21 dq10 141 dq15 80 dq32 200 dq37 22 dq11 142 vss 81 dq33 201 vss 23 vss 143 dq20 82 vss 202 dm4, dqs13 24 dq16 144 dq21 83 dqs4 203 dqs13 25 dq17 145 vss 84 dqs4 204 vss 26 vss 146 dm2, dqs11 85 vss 205 dq38 27 dqs2 147 dqs11 86 dq34 206 dq39 28 dqs2 148 vss 87 dq35 207 vss 29 vss 149 dq22 88 vss 208 dq44 30 dq18 150 dq23 89 dq40 209 dq45 31 dq19 151 vss 90 dq41 210 vss 32 vss 152 dq28 91 vss 211 dm5, dqs14 33 dq24 153 dq29 92 dqs5 212 dqs14 34 dq25 154 vss 93 dqs5 213 vss 35 vss 155 dm3, dqs12 94 vss 214 dq46 36 dqs3 156 dqs12 95 dq42 215 dq47 37 dqs3 157 vss 96 dq43 216 vss 38 vss 158 dq30 97 vss 217 dq52 39 dq26 159 dq31 98 dq48 218 dq53 40 dq27 160 vss 99 dq49 219 vss
hys72txx0xxgr registered ddr2 sdram-modules infineon technologies 6 2.04 pin configuration (cont?d) 1.6 pin locations pin# symbol pin# symbol pin# symbol pin# symbol 41 vss 161 cb4 100 vss 220 nc 42 cb0 162 cb5 101 sa2 221 nc 43 cb1 163 vss 102 nc 222 vss 44 vss 164 dm8, dqs17 103 vss 223 dm6, dqs15 45 dqs8 165 dqs17 104 dqs6 224 dqs15 46 dqs8 166 vss 105 dqs6 225 vss 47 vss 167 cb6 106 vss 226 dq54 48 cb2 168 cb7 107 dq50 227 dq55 49 cb3 169 vss 108 dq51 228 vss 50 vss 170 vddq 109 vss 229 dq60 51 vddq 171 nc, cke1 110 dq56 230 dq61 52 cke0 172 vdd 111 dq57 231 vss 53 vdd 173 nc 112 vss 232 dm7, dqs16 54 nc 174 nc 113 dqs7 233 dqs16 55 nc 175 vddq 114 dqs7 234 vss 56 vddq 176 a12 115 vss 235 dq62 57 a11 177 a9 116 dq58 236 dq63 58 a7 178 vdd 117 dq59 237 vss 59 vdd 179 a8 118 vss 238 vddspd 60 a5 180 a6 119 sda 239 sa0 120 scl 240 sa1 65 64 120 pin 1 front 184 185 240 pin 121 backside 240 pin modules (mo-237)
hys72txx0xxgr registered ddr2 sdram-modules infineon technologies 7 2.04 1.7 registered dimm input/output functional description symbol type polarity function ck0, ck 0 input cross point the system clock inputs. all address and command lines are sampled on the cross point of the rising edge of ck and the falling edge of ck . an on-board dll circuit is driven from the clock inputs and output timing for read operations is synchronized to the input clock. cke[1:0] input active high cke high activates and cke low deactivates internal clock signals and device input buffers and output drivers of the sdrams. taking cke low provides precharge power-down and self-refresh operation (all banks idle), or active power-down (row active in any bank). cs [1:0] input active low enables the associated sdram command decoder when low and disables decoder when high. when decoder is disabled, new commands are ignored and previous operations con- tinue. the input signals also disable all outputs (except cke and odt) of the register(s) on the dimm when both inputs are high. when both cs [1:0] are high, all register outputs (except ck, odt and chip select) remain in the previous state. odt[1:0] input active high on-die termination control signals ras , cas , we input active low when sampled at the positive edge of the clock, ras , cas and we define the operation to be executed by the sdram. dm[8:0] input active high masks write data when high, issued concurrently with input data. ba[1:0] input - selects which internal sdram memory bank is activated a[12:0] input - during bank activate command cycle, address defines the row address. during a read or write command cycle, address defines the column address. in addition to the column address, a10(=ap) is used to invoke auto-precharge operation at the end of the burst read or write cycle. if ap is high, auto precharge is selected and ba[1:0] defines the bank to be precharged. if ap is low, auto-precharge is disabled. during a precharge command cycle, ap is used in conjunction with ba[1:0] to control which bank(s) to precharge. if ap is high, all banks will be precharged regardless of the state of ba[1:0]. if ap is low, ba[1:0] are used to define which bank to precharge. dq[63:0], cb[7:0] i/o - data and check bit input /output pins. dqs[17:0], dqs [17:0] i/o cross point the data strobes, associated with one data byte, source with data transfer. in write mode, the data strobe is sourced by the controller and is centered in the data window. in read mode the data strobe is sources by the ddr2 sdram and is sent at the leading edge of the data window. dqs signals are complements, and timing is relative to the crosspoint of respective dqs and dqs . if the module is to be operated in single ended strobe mode, all dqs signals must be tied on the system board to vss and ddr2 sdram mode registers programmed appropriately. sa[2:0] input - these signals are tied at the system planar to ei ther vss or vddspd to configure the serial spd eeprom address range sda i/o - this bidirectional pin is used to transfer data into and out of the spd eeprom. a resistor maybe connected from the sda bus line to vd dspd on the system planar to act as a pull- up. scl input - this signal is used to clock data into the spd eeprom. a resistor maybe connected from the scl bus line to vddspd on the system planar to act as a pull-up. reset input - the reset pin is connected to the rst pin on the register and to the oe pin on the pll. when low, all register outputs will be driven low and the pll clocks to the drams and the register(s) will be set to low level. the pll will remain synchronized with the input clock. v dd, v ss supply - power and ground for the ddr sdram input buffers and core logic. v ref supply - reference voltage for the sstl-18 inputs. v ddspd supply - serial eeprom positive power supply, wired to a separated power pin at the connector which supports from 1.7 volt to 3.6 volt. note: cs1 , odt1 and cke1 are used on dual rank modules only.
hys72txx0xxgr registered ddr2 sdram-modules infineon technologies 8 2.04 2.0 block diagrams (cont?d) 2.1 one rank 32m x 72 (256 mbyte) ddr2 sdram dimm module (x8 components) hys72t32000gr on raw card a dm1/dqs10 dqs1 dqs1 ck0 ck 0 p l l pck0-pck6,pck8,pck9 ck : sdrams d0-d8 reset oe pck7 -> ck : register pck7 > ck : register ba0-ba1 rba0 -rba1 -> b a0-ba1 : sdrams d0-d8 a0 -a12 ra0 -ra 12-> a0 -a 12: sdr a ms d0 -d8 ras rra s -> ras : sd rams d0- d 8 cs0 * rs 0 -> c s : sdrams d0-d8 cas rc as -> c a s : sdrams d0-d8 cke0 rck e0 -> cke : sdra d0-d8 we rw e -> we : sdrams d0-d8 1:1 odt0 rodt0 -> odt 0: sdrams d0-d8 pck7 cb4 cb5 cb6 cb7 cb0 cb1 cb2 cb3 dq20 dq21 dq22 dq23 dq16 dq17 dq18 dq19 dq12 dq13 dq14 dq15 dq8 dq9 dq10 dq11 dq28 dq29 dq30 dq31 dq24 dq25 dq26 dq27 pck0-pck6, pck8,pck9 ck : sdrams d0-d8 rst reset pck 7 d1 i/o 0 i/o 1 i/o 2 i/o 3 i/o 4 i/o 5 i/o 6 i/o 7 d2 i/o 0 i/o 1 i/o 2 i/o 3 i/o 4 i/o 5 i/o 6 i/o 7 d3 i/o 0 i/o 1 i/o 2 i/o 3 i/o 4 i/o 5 i/o 6 i/o 7 d8 i/o 0 i/o 1 i/o 2 i/o 3 i/o 4 i/o 5 i/o 6 i/o 7 rs0 dm2/dqs11 dqs2 dqs0 dm3/dqs12 dqs3 dqs3 dm8/dqs17 dqs8 dqs8 dq4 dq5 dq6 dq7 dq0 dq1 dq2 dq3 d0 i/o 0 i/o 1 i/o 2 i/o 3 i/o 4 i/o 5 i/o 6 i/o 7 dm0/dqs9 dqs0 dqs0 dq36 dq37 dq38 dq39 dq32 dq33 dq34 dq35 d4 i/o 0 i/o 1 i/o 2 i/o 3 i/o 4 i/o 5 i/o 6 i/o 7 dm4/dqs13 dqs4 dqs4 dq44 dq45 dq46 dq47 dq40 dq41 dq42 dq43 d5 i/o 0 i/o 1 i/o 2 i/o 3 i/o 4 i/o 5 i/o 6 i/o 7 dm5/dqs14 dqs5 dqs5 dq52 dq53 dq54 dq55 dq48 dq49 dq50 dq51 d6 i/o 0 i/o 1 i/o 2 i/o 3 i/o 4 i/o 5 i/o 6 i/o 7 dm6/dqs15 dqs6 dqs6 dq60 dq61 dq62 dq63 dq56 dq57 dq58 dq59 d7 i/o 0 i/o 1 i/o 2 i/o 3 i/o 4 i/o 5 i/o 6 i/o 7 dm7/dqs16 dqs7 dqs7 cs dqs dqs dm/ rdqs nu/ rdqs cs dqs dqs dm/ rdqs nu/ rdqs cs dqs dqs dm/ rdqs nu/ rdqs cs dqs dqs dm/ rdqs nu/ rdqs cs dqs dqs dm/ rdqs nu/ rdqs cs dqs dqs dm/ rdqs nu/ rdqs cs dqs dqs dm/ rdqs nu/ rdqs cs dqs dqs dm/ rdqs nu/ rdqs cs dqs dqs dm/ rdqs nu/ rdqs r e g i s t e r notes: 1. dq-to-i/o wiring may be changed within a byte 2. unless otherwise noted, resistor values are 22 ohms a0 serial pd a1 a2 sa0 sa1 sa2 scl sda wp v dd, v ss d0 - d8 d0 - d8 v ddq d0 - d8 vref v ddspd serial pd dqs9 dqs10 dqs11 dqs12 dqs17 dqs16 dqs15 dqs14 dqs13 *) cs0 connects to dcs and vdd connects to csr on the registers
hys72txx0xxgr registered ddr2 sdram-modules infineon technologies 9 2.04 block diagrams (cont?d) 2.2 64m x 72 (512 mbyte) two rank ddr2 sdram dimm modules (x8 components) HYS72T64020GR on raw card b cke0 rck e0 -> cke : sdrams d0-d8 dq36 dq37 dq38 dq39 dq32 dq33 dq34 dq35 d4 i/o 0 i/o 1 i/o 2 i/o 3 i/o 4 i/o 5 i/o 6 i/o 7 dm4/dqs13 dqs4 dqs4 dq44 dq45 dq46 dq47 dq40 dq41 dq42 dq43 d5 i/o 0 i/o 1 i/o 2 i/o 3 i/o 4 i/o 5 i/o 6 i/o 7 dm5/dqs14 dqs5 dqs5 dq52 dq53 dq54 dq55 dq48 dq49 dq50 dq51 d6 i/o 0 i/o 1 i/o 2 i/o 3 i/o 4 i/o 5 i/o 6 i/o 7 dm6/dqs15 dqs6 dqs6 dq60 dq61 dq62 dq63 dq56 dq57 dq58 dq59 d7 i/o 0 i/o 1 i/o 2 i/o 3 i/o 4 i/o 5 i/o 6 i/o 7 dm7/dqs16 dqs7 dqs7 dqs16 cs dqs dqs dm/ rdqs nu/ rdqs cs dqs dqs dm/ rdqs nu/ rdqs cs dqs dqs dm/ rdqs nu/ rdqs cs dqs dqs dm/ rdqs nu/ rdqs dm1/dqs10 dqs1 dqs1 cb4 cb5 cb6 cb7 cb0 cb1 cb2 cb3 dq20 dq21 dq22 dq23 dq16 dq17 dq18 dq19 dq12 dq13 dq14 dq15 dq8 dq9 dq10 dq11 dq28 dq29 dq30 dq31 dq24 dq25 dq26 dq27 d1 i/o 0 i/o 1 i/o 2 i/o 3 i/o 4 i/o 5 i/o 6 i/o 7 d2 i/o 0 i/o 1 i/o 2 i/o 3 i/o 4 i/o 5 i/o 6 i/o 7 d3 i/o 0 i/o 1 i/o 2 i/o 3 i/o 4 i/o 5 i/o 6 i/o 7 d8 i/o 0 i/o 1 i/o 2 i/o 3 i/o 4 i/o 5 i/o 6 i/o 7 rs0 dm2/dqs11 dqs2 dqs0 dm3/dqs12 dqs3 dqs3 dm0/dqs17 dqs8 dqs8 dqs17 dq4 dq5 dq6 dq7 dq0 dq1 dq2 dq3 dm0/dqs9 dqs0 dqs0 cs dqs dqs dm/ rdqs nu/ rdqs cs dqs dqs dm/ rdqs nu/ rdqs cs dqs dqs dm/ rdqs nu/ rdqs cs dqs dqs dm/ rdqs nu/ rdqs d0 i/o 0 i/o 1 i/o 2 i/o 3 i/o 4 i/o 5 i/o 6 i/o 7 cs dqs dqs dm/ rdqs nu/ rdqs d9 i/o 0 i/o 1 i/o 2 i/o 3 i/o 4 i/o 5 i/o 6 i/o 7 cs dqs dqs dm/ rdqs nu/ rdqs d10 i/o 0 i/o 1 i/o 2 i/o 3 i/o 4 i/o 5 i/o 6 i/o 7 cs dqs dqs dm/ rdqs nu/ rdqs d11 i/o 0 i/o 1 i/o 2 i/o 3 i/o 4 i/o 5 i/o 6 i/o 7 cs dqs dqs dm/ rdqs nu/ rdqs d12 i/o 0 i/o 1 i/o 2 i/o 3 i/o 4 i/o 5 i/o 6 i/o 7 cs dqs dqs dm/ rdqs nu/ rdqs d17 i/o 0 i/o 1 i/o 2 i/o 3 i/o 4 i/o 5 i/o 6 i/o 7 cs dqs dqs dm/ rdqs nu/ rdqs d13 i/o 0 i/o 1 i/o 2 i/o 3 i/o 4 i/o 5 i/o 6 i/o 7 cs dqs dqs dm/ rdqs nu/ rdqs d14 i/o 0 i/o 1 i/o 2 i/o 3 i/o 4 i/o 5 i/o 6 i/o 7 cs dqs dqs dm/ rdqs nu/ rdqs d15 i/o 0 i/o 1 i/o 2 i/o 3 i/o 4 i/o 5 i/o 6 i/o 7 cs dqs dqs dm/ rdqs nu/ rdqs d16 i/o 0 i/o 1 i/o 2 i/o 3 i/o 4 i/o 5 i/o 6 i/o 7 cs dqs dqs dm/ rdqs nu/ rdqs rs1 dq-to-i/o wiring may be changed within a byte dq/dqs/dqs, adress and control resistors are 22 ohms ba0-ba1 a0 -a12 ras cs1 * cas we 1:2 a0 serial pd a1 a2 sa0 sa1 sa2 scl sda wp v dd, v ss d0 - d17 v ddq vref v ddspd serial pd d0 - d17 d0 - d17 r e g i s t e r rba0 -rba1 -> b a0-ba1 : sdrams d0-d17 ra0 -ra 12-> a0 -a 12: sdr a ms rra s -> ras : sd rams rs 1 -> c s : sdrams d9-d17 rcas -> c a s : sdrams rw e -> we : sdrams cs0 * rs 0 -> c s : sdrams d0-d8 d0-d17 d0-d17 d0-d17 d0-d17 pck7 rst reset pck 7 odt0 rodt0 -> odt : sdrams d0-d8 cke1 rck e1 -> cke : sdrams d9-d17 odt1 rodt1 -> odt : sdrams d9-d17 *) cs0 connects to crs, cs1 connects to csr on a register. cs1 connects to dcs and cs0 connects to csr on another register. reset, pck7 and pck7 connect to bother registers. other signals connect to one of two registers. ck 0 ck 0 p l l pck0-pck6, pck8,pck9 ck : sdrams d0-d17 reset oe pck7 -> ck : register pck7 > ck : register pck0-pck6, pck8,pck9 ck : sdrams d0-d17 dqs9 dqs10 dqs11 dqs12 dqs15 dqs14 dqs13
hys72txx0xxgr registered ddr2 sdram-modules infineon technologies 10 2.04 block diagrams (cont?d) 2.3 one rank 64m x 72 (512 mbyte) ddr2 sdram dimm modules (x4 components) hys72t64001gr on raw card c odt0 rodt0 -> odt : sdrams d0-d17 rs0 vss dqs0 dqs0 d0 cs dqs dqs dm i/o 0 i/o 1 i/o 2 i/o 3 dq3 dq0 dq1 dq2 dqs1 d1 cs dqs dqs dm i/o 0 i/o 1 i/o 2 i/o 3 dq11 dq8 dq9 dq10 dqs2 d2 cs dqs dqs dm i/o 0 i/o 1 i/o 2 i/o 3 dq19 dq16 dq17 dq18 dqs3 d3 cs dqs dqs dm i/o 0 i/o 1 i/o 2 i/o 3 dq27 dq24 dq25 dq26 dqs4 d4 cs dqs dqs dm i/o 0 i/o 1 i/o 2 i/o 3 dq35 dq32 dq33 dq34 dqs5 d5 cs dqs dqs dm i/o 0 i/o 1 i/o 2 i/o 3 dq43 dq40 dq41 dq42 dqs6 d6 cs dqs dqs dm i/o 0 i/o 1 i/o 2 i/o 3 dq51 dq48 dq49 dq50 dqs7 d7 cs dqs dqs dm i/o 0 i/o 1 i/o 2 i/o 3 dq59 dq56 dq57 dq58 dqs8 d8 cs dqs dqs dm i/o 0 i/o 1 i/o 2 i/o 3 cb3 cb0 cb1 cb2 dqs9 dqs9 d9 cs dqs dqs dm i/o 0 i/o 1 i/o 2 i/o 3 dq7 dq4 dq5 dq6 d10 cs dqs dqs dm i/o 0 i/o 1 i/o 2 i/o 3 dq15 dq12 dq13 dq14 d11 cs dqs dqs dm i/o 0 i/o 1 i/o 2 i/o 3 dq23 dq20 dq21 dq22 d12 cs dqs dqs dm i/o 0 i/o 1 i/o 2 i/o 3 dq31 dq28 dq29 dq30 d13 cs dqs dqs dm i/o 0 i/o 1 i/o 2 i/o 3 dq39 dq36 dq37 dq38 d14 cs dqs dqs dm i/o 0 i/o 1 i/o 2 i/o 3 dq47 dq44 dq45 dq46 d15 cs dqs dqs dm i/o 0 i/o 1 i/o 2 i/o 3 dq55 dq52 dq53 dq54 d16 cs dqs dqs dm i/o 0 i/o 1 i/o 2 i/o 3 dq63 dq60 dq61 dq62 d17 cs dqs dqs dm i/o 0 i/o 1 i/o 2 i/o 3 cb7 cb4 cb5 cb6 dqs0 dqs2 dqs3 dqs4 dqs5 dqs6 dqs7 dqs8 dqs10 dqs10 dqs11 dqs11 dqs12 dqs12 dqs13 dqs13 dqs14 dqs14 dqs15 dqs15 dqs16 dqs16 dqs17 dqs17 dq-to-i/o wiring may be changed within per nibble unless otherwise noted, resistor values are 22 ohms *) cs0 connects to dcs of register 1 and csr of register 2, csr of register 1 and dcs of register 2 connects to vdd **) reset, pck7 and pck7 connet to both registers. other signals connect to one of two registers. a0 serial pd a1 a2 sa0 sa1 sa2 scl sda wp v dd, v ss d0 - d17 v ddq vref v ddspd serial pd d0 - d17 d0 - d17 ck 0 ck 0 p l l pck0-pck6, pck8,pck9 ck : sdrams d0-d17 reset oe pck7 -> ck : register pck7 > ck : register pck0-pck6, pck8,pck9 ck : sdrams d0-d17 cke0 rck e0 -> cke : sdrams ba0-ba1 a0 -a12 ras cas we 1:2 r e g i s t e r rba0 -rba1 -> b a0-ba1 : sdrams ra0 -ra 12-> a0 -a 12: sdr a ms rra s -> ras : sd rams rcas -> c a s : sdrams rw e -> we : sdrams cs0 * rs 0 -> c s : sdrams d0-d17 d0-d17 d0-d17 d0-d17 d0-d17 pck7 rst reset pck 7 d0-d17
hys72txx0xxgr registered ddr2 sdram-modules infineon technologies 11 2.04 3.0 absolute maximum ratings 3.1 operating temperature range 3.2 supply voltage levels and dc operating conditions parameter symbol limit values unit min. max. voltage on any pins relative to v ss v in, v out ? 0.5 2.3 v voltage on v dd relative to v ss v dd ? 1.0 2.3 v voltage on v dd q relative to v ss v ddq ? 0.5 2.3 storage temperature range t stg -55 +100 o c stresses greater than those listed under ?absolute maximum ratings? may cause permanent damage to the device. this is a stress rating only and functional operation of the device at these or any other conditions above those indicated in the operati onal sections of this specification is not implied. exposure to absolute maximum rating conditions for extended periods may affect r eli- ability. parameter symbol limit values unit notes min. max. dimm module operating temperature range (ambient) topr 0+55 o c dram component case temperature range tcase 0+95 o c1 - 4 1. dram component case temperature is the surface temperatur e in the center on the top side of any of the drams. for measurement conditions, please refer to the jedec document jesd51-2. 2. within the dram component case temperature range all dram specification will be supported. 3. above 85 o c dram case temperature the auto-refresh command interval has to be reduced to trefi = 3.9 s. 4. self-refresh period is hard-coded in the drams and therefore it is imperative that the system ensures the dram is below 85 o c case temperature before initiating self-refresh operation. parameter symbol limit values unit notes min. nom. max. device supply voltage v dd 1.7 1.8 1.9 v - output supply voltage v ddq 1.7 1.8 1.9 v 1) input reference voltage v ref 0.49 x v ddq 0.5 x v ddq 0.51 x v ddq v2) eeprom supply voltage v ddspd 1.7 ? 3.6 v dc input logic high v ih (dc) v ref +0.125 ? v ddq +0.3 v dc input logic low v il (dc) ? 0.30 ? v ref ?0.125 v in / output leakage current i l ? 5 ? 5 a3) 1 under all conditions, v ddq must be less than or equal to v dd 2 peak to peak ac noise on v ref may not exceed 2% v ref (dc) . v ref is also expected to track noise variations in v ddq . 3 for any pin on the dimm connector under test input of 0 v v in v ddq +0.3v.
hys72txx0xxgr registered ddr2 sdram-modules infineon technologies 12 2.04 4.0 i dd specifications and conditions 4.1 256mbyte registered module hys7 2t32000gr (one rank, nine components x8) 4.2 512 mbyte registered module HYS72T64020GR (two ranks, eighteen components x8) 256 mbyte hys72t32000gr pc2-3200 ?-5? pc2-4200 ?-3.7? pc2-5300 ?-3? symbol parameter / condition max. max. max. unit note i dd0 operating current 700 828 957 ma 1 i dd1 operating current 745 873 1002 ma 1 i dd2p precharge pd standby current 286 369 453 ma 1 i dd2n precharge standby current 502 657 822 ma 1 i dd2q precharge quiet standby current 430 558 687 ma 1 i dd3p(0) active pd standby current 367 477 597 ma 1 i dd3p(1) lp active pd standby current 286 369 867 ma 1 i dd3n active standby current 520 648 777 ma 1 i dd4r operating current burst read 790 963 1137 ma 1 i dd4w operating current burst write 880 1098 1317 ma 1 i dd5b auto-refresh current (trfcmin.) 970 1098 1227 ma 1 i dd5d auto-refresh current (trefi) 304 387 471 ma 1 i dd6 self-refresh current 36 36 36 ma 1 i dd7 operating current 1375 1548 1722 ma 1 note: 1) calculated values from component data. odt disabled. idd1, idd4r, and idd7 are defined with the outputs disabled. currents includes registers and pll. 512 mbyte HYS72T64020GR pc2-3200 ?-5? pc2-4200 ?-3.7? pc2-5300 ?-3? symbol parameter / condition max. max. max. unit note i dd0 operating current 854 1021 1190 ma 1, 2 i dd1 operating current 899 1066 1235 ma 1, 2 i dd2p precharge pd standby current 440 562 686 ma 1, 3 i dd2n precharge standby current 872 1138 1424 ma 1, 3 i dd2q precharge quiet standby current 728 940 1154 ma 1, 3 i dd3p(0) active pd standby current 602 778 974 ma 1, 3 i dd3p(1) lp active pd standby current 440 562 686 ma 1, 3 i dd3n active standby current 908 1120 1334 ma 1, 3 i dd4r operating current burst read 944 1156 1370 ma 1, 2 i dd4w operating current burst write 1034 1291 1550 ma 1, 2 i dd5b auto-refresh current (trfcmin.) 1126 1291 1460 ma 1, 2 i dd5d auto-refresh current (trefi) 476 598 722 ma 1, 3 i dd6 self-refresh current 72 72 72 ma 1, 3 i dd7 operating current 1529 1741 1955 ma 1, 2 notes: 1) calculated values from component data. odt disabled. idd1, idd4r, and idd7 are defined with the outputs disabled. currents includes registers and pll. 2) the other rank is in idd2p precharge power-down standby current mode 3) both ranks are in the same idd current mode
hys72txx0xxgr registered ddr2 sdram-modules infineon technologies 13 2.04 4.3 512 mbyte registered module hys72t64001gr (one rank, eighteen components x4) 512 mbyte hys72t64001gr pc2-3200 ?-5? pc2-4200 ?-3.7? pc2-5300 ?-3? symbol parameter / condition max. max. max. unit note i dd0 operating current 1268 1480 1694 ma 1 i dd1 operating current 1358 1570 1784 ma 1 i dd2p precharge pd standby current 440 562 686 ma 1 i dd2n precharge standby current 872 1138 1424 ma 1 i dd2q precharge quiet standby current 728 940 1154 ma 1 i dd3p(0) active pd standby current 602 778 974 ma 1 i dd3p(1) lp active pd standby current 440 562 686 ma 1 i dd3n active standby current 908 1120 1334 ma 1 i dd4r operating current burst read 1448 1750 2054 ma 1 i dd4w operating current burst write 1628 2020 2414 ma 1 i dd5b auto-refresh current (trfcmin.) 1808 2020 2234 ma 1 i dd5d auto-refresh current (trefi) 476 598 722 ma 1 i dd6 self-refresh current 72 72 72 ma 1 i dd7 operating current 2618 2920 3224 ma 1 note: 1) calculated values from component data. odt disabled. idd1, idd4r, and idd7 are defined with the outputs disabled. currents includes registers and pll.
hys72txx0xxgr registered ddr2 sdram-modules infineon technologies 14 2.04 4.4 i dd measurement conditions symbol parameter/condition i dd0 operating current - one bank active - precharge tck = tck(idd), trc = trc(idd), tras = trasmin(idd), cke is high, cs is high between valid commands. address and control inputs are switching, databus inputs are switching. i dd1 operating current - one bank active - read - precharge iout = 0 ma, bl = 4, tck = tck(idd), trc = trc(idd), tr as = trasmin(idd),trcd = trcd(idd),al = 0, cl = cl(idd); cke is high, cs is high between valid commands. address and control inputs are switching, databus inputs are switching. i dd2p precharge power-down current: all banks idle; cke is low; tck = tck(idd); other control and address inputs are stable, data bus inputs are floating. i dd2n precharge standby current : all banks idle; cs is high; cke is high; tck = tck(idd); other control and address inputs are switching, data bus inputs are switching. i dd2q precharge quiet standby current : all banks idle; cs is high; cke is high; tck = tck(idd); other control and address inputs are stable, data bus inputs are floating. i dd3p(0) active power-down current : all banks open; tck = tck(idd), cke is low; other control and address inputs are sta- ble, data bus inputs are floating. mrs a12 bit is set to ?0? (fast power-down exit); i dd3p(1) active power-down current : all banks open; tck = tck(idd), cke is low; other control and address inputs are sta- ble, data bus inputs are floating. mrs a12 bit is set to ?1? (slow power-down exit); i dd3n active standby current : all banks open; tck = tck(idd); tras = trasmax(idd); trp = trp(idd),cke is high; cs is high between valid commands. other control and address inputs are switching, data bus inputs are switching. i dd4r operating current - burst read: all banks open; continuous burst reads; bl = 4;al = 0, cl = cl(idd); tck = tck(idd); tras = trasmax(idd), trp = trp(idd); cke is high, cs is high between valid commands. address inputs are switching; data bus inputs are switching; iout = 0ma. i dd4w operating current - burst write: all banks open; continuous burst writes; bl = 4; al = 0, cl = cl(idd); tck = tck(idd); tras = trasmax(idd), trp = trp(idd); cke is high, cs is high between valid commands. address inputs are switching; data bus inputs are switching; i dd5b burst auto-refresh current : tck = tck(idd), refresh command every tr fc = trfc(idd) interval, cke is high, cs is high between valid commands, other control and address inputs are switching, data bus inputs are switching. i dd5d distributed auto-refresh current : tck = tck(idd), refresh command every trfc = trefi interval, cke is low and cs is high between valid commands, other control and address inputs are switching, data bus inputs are switching. i dd6 self-refresh current : cke 0.2v; external clock off, ck and ck at 0v; other control and address inputs are floating, data bus inputs are floating. reset = low. i dd6 current values are guaranteed up to tcase of 85 o c max. i dd7 all bank interleave read current: 1. all banks interleaving reads, iout = 0 ma; bl = 4, cl=cl(idd), al = trcd(idd) -1*tck(idd); tck = tck(idd), trc = trc(idd), trrd = trrd(idd); cke is high, cs is high between valid commands, address bus inputs are stable during deselects; data bus is switching. 2. timing pattern: - ddr2 -400 : a0 ra0 a1 ra1 a2 ra2 a3 ra3 d d d d - ddr2 -533 : a0 ra0 d a1 ra1 d a2 ra2 d a3 ra3 d d d d d - ddr2 -667 : a0 ra0 d d a1 ra1 d d a2 ra2 d d a3 ra3 d d d d d 3. legend: a = activate, ra = read with auto-precharge, d=deselect notes: 1. idd specifications are tested after the device is properly initialized and idd parameter are specified with odt disabled. 2. definitions for idd: low is defined as vin <= vil(ac)max; high is defined as vin >= vih(ac)min. stable is defined as inputs ar e stable at a high or low level. floating is defined as inputs are vref = vddq / 2. switching is defined as: inputs are changing between high and low every other clo ck (once per two cycles) for address and control signals, and inputs changing between h igh and low every other data transfer (once pe r cycle) for dq signals not including mask or strobes. 3. idd1, idd4r, and idd7 current measurements are defined with the outputs disabled (iout = 0 ma). to achieve this on module le vel the output buffers can be disabled using an emrs(1) (extended mode register command) by setting a12 bit to high. 3. for two rank modules: for all active current measurement s the other rank is in precharge power-down mode idd2p 4. reset signal is high for all currents, except for idd6 ?self refresh?. 5. all current measurements includes register and pll current consumption.
hys72txx0xxgr registered ddr2 sdram-modules infineon technologies 15 2.04 4.5 i dd measurement conditions (cont?d) for testing the idd parameters, the following timing parameters are used: 4.5 odt (on die termination) current the odt function adds additional current consumption to the ddr2 sdram when enabled by the emrs(1). depending on address bits a6 & a2 in the emrs(1) a ?week? or ?strong? termination can be selected. the cur- rent consumption for any terminated input pin, depends on the input pin is in tri-state or driving ?0? or ?1?, as long a odt is enabled during a given period of time. odt current per terminated pin: parameter symbol -5 pc2-3200 -3.7 pc2-4200 -3 pc2-5300 unit 3-3-3 4-4-4 4-4-4 cas latency cl(idd) 3 4 4 tck clock cycle time tck(idd) 5 3.75 3 ns active to read or write delay trcd(idd) 15 15 12 ns active to active / auto-refresh command period trc(idd) 60 60 57 ns active bank a to active bank b command delay trrd(idd) 7.5 7.5 7.5 ns active to precharge command trasmin(idd) 45 45 45 ns trasmax(idd) 70000 70000 70000 ns precharge command period trp(idd) 15 15 12 ns auto-refresh to active / auto-refresh command period trfc(idd) 75 75 75 ns average periodic refresh interval trefi 7.8 7.8 7.8 s emrs(1) state min. typ. max. unit enabled odt current per dq added iddq current for odt enabled; odt is high; data bus inputs are floating iodto a6 = 0, a2 = 1 5 6 7.5 ma/dq a6 = 1, a2 = 0 2.5 3 3.75 ma/dq active odt current per dq added iddq current for odt enabled; odt is high; worst case of data bus inputs are stable or switching. iodtt a6 = 0, a2 = 1 10 12 15 ma/dq a6 = 1, a2 = 0 5 6 7.5 ma/dq note: for power consumption calculations the odt duty cycle has to be taken into account
hys72txx0xxgr registered ddr2 sdram-modules infineon technologies 16 2.04 5.0 electrical characteristics & ac timings 5.1 ac timing parameter by speed grade (component level data, for reference only) symbol parameter -5 ddr2 -400 -3.7 ddr2 -533 -3 ddr2 -667 unit min max min max min max t ac dq output access time from ck / ck ? 600 + 600 -500 +500 -450 +450 ps t dqsck dqs output access time from ck / ck ? 500 + 500 ? 450 + 450 -400 +400 ps t ch ck, ck high-level width 0.45 0.55 0.45 0.55 0.45 0.55 t ck t cl ck, ck low-level width 0.45 0.55 0.45 0.55 0.45 0.55 t ck t hp clock half period min. (t cl, t ch) min. (t cl, t ch) min. (t cl, t ch) t ck clock cycle time cl = 3 5000 8000 5000 8000 5000 8000 ps cl = 4 & 5 5000 8000 3750 8000 3000 8000 ps t is address and control input setup time 600 - 600 - tbd. - ps t ih address and control input hold time 600 - 600 - tbd. - ps t ds dq and dm input setup time 400 - 350 - 300 - ps t dh dq and dm input hold time 400 - 350 - 300 - ps t ipw control and addr. input pulse width (each input) 0.6 - 0.6 - 0.6 - t ck t dipw dq and dm input pulse width (each input) 0.35 - 0.35 - 0.35 - t ck t hz data-out high-impedance time from ck / ck -tacmax-tacmax-tacmaxps t lz(dq) dq low-impedance from ck / ck 2*tacmin tacmax 2*tacmin tacmax 2*tacmin tacmax ps t lz(dqs) dqs low-impedance from ck / ck tacmin tacmax tacmin tacmax tacmin tacmax ps t dqsq dqs-dq skew (for dqs & associated dq signals) -350-300-250ps t qhs data hold skew factor - 450 - 400 - 350 ps t qh data output hold time from dqs t hp -t qhs -t hp -t qhs -t hp -t qhs - t dqss write command to 1st dqs latching transition wl -0.25 wl +0.25 wl -0.25 wl +0.25 wl -0.25 wl +0.25 t ck t dqsl,h dqs input low (high) pulse width (write cycle) 0.35 - 0.35 - 0.35 - t ck t dss dqs falling edge to clk setup time (write cycle) 0.2 - 0.2 - 0.2 - t ck t dsh dqs falling edge hold time from clk (write cycle) 0.2 - 0.2 - 0.2 - t ck t mrd mode register set command cycle time 2 - 2 - 2 - t ck t wpre write preamble 0.25 - 0.25 - 0.35 - t ck t wpst write postamble 0.40 0.60 0.40 0.60 0.40 0.60 t ck t rpre read preamble 0.9 1.1 0.9 1.1 0.9 1.1 t ck t rpst read postamble 0.400.600.400.600.400.60t ck t ras active to precharge command 45 70000 45 70000 45 70000 ns t rc active to active/auto-refresh command period 60 - 60 - 57 - ns t rfc auto-refresh to active/auto-refresh command period 75 - 75 - 75 - ns
hys72txx0xxgr registered ddr2 sdram-modules infineon technologies 17 2.04 5.2 odt ac electrical characteristics and operating conditions (all speed bins) t rcd active to read or write delay (with and without auto-precharge) delay 15 - 15 - 12 - ns t rp precharge command period 15 - 15 - 12 - ns t rrd active bank a to active bank b command (1k page size) 7.5 - 7.5 - 7.5 - ns t ccd cas a to cas b command period 2-2-2-t ck t wr write recovery time 15 - 15 - 15 - ns t dal auto precharge write recovery + precharge time wr+trp - wr+trp - wr+trp - t ck t wtr internal write to read command delay 10 - 7.5 - 7.5 - ns t rtp internal read to precharge command delay 7.5 - 7.5 - 7.5 - ns t xard exit power down to any valid command (other than nop or deselect) 2-2-2-t ck t xards exit active power-down mode to read command (slew exit, lower power) 6 - al - 6 - al - 6 - al - t ck t xp exit precharge power-down to any valid com- mand (other than nop or deselect) 2-2-2-t ck t xsrd exit self-refresh to read command 200 - 200 - 200 - t ck t xsnr exit self-refresh to non-read command trfc + 10 - trfc + 10 - trfc + 10 - ns t cke cke minimum high and low pulse width 3 - 3 - 3 - t ck t oit ocd drive mode output delay 0 12 0 12 0 12 ns t delay minimum time clocks remain on after cke asynchronously drops low tis+tck +tih - tis+tck +tih - tis+tck +tih -ns t refi average periodic refresh interval 0 o c - 85 o c - 7.8 - 7.8 - 7.8 s 85 o c - 95 o c - 3.9 - 3.9 - 3.9 1. for details and notes see the relevant infineon component datasheet 2. timing definition and values for tis, tih, tds and tdh may change due to actual jedec work. this may also effect the spd cod e for these parameters. symbol parameter / condition min. max. units t aond odt turn-on delay 2 2 t ck t aon odt turn-on ddr2-400/533 tac(min) tac(max) + 1 ns ns ddr2-667 tac(min) tac(max) + 0.7 ns t aonpd odt turn-on (power-down modes) tac(min) + 2 ns 2 tck + tac(max) + 1 ns ns t aofd odt turn-off delay 2.5 2.5 t ck t aof odt turn-off tac(min) tac(max) + 0.6 ns ns t aofpd odt turn-off delay (power-down modes) tac(min) + 2 ns 2.5 tck + tac(max) + 1 ns ns t anpd odt to power down mode entry latency 3 - t ck t axpd odt power down exit latency 8 - t ck symbol parameter -5 ddr2 -400 -3.7 ddr2 -533 -3 ddr2 -667 unit min max min max min max
hys72txx0xxgr registered ddr2 sdram-modules infineon technologies 18 2.04 6.0 serial presence detect codes for registered dimm modules byte# description speed grade spd entry value hex value note: ?-5 ? := ddr2-3200 (ddr2-400) ?-3.7? := ddr2-4200 (ddr2-533) ?-3 ? := ddr2-5300 (ddr2-667) hys72t32000gr HYS72T64020GR hys72t64001gr 0 number of spd bytes all 128 80 1 total bytes in serial pd all 256 08 2 memory type all ddr2-sdram 08 3 number of row addresses all 13 0d 4 number of column addresses all 10 / 11 0a 0a 0b 5 number of dimm ranks, package and height all 1 / 2 60 61 60 6 module data width all x72 48 7 not used all not used 00 8 module interface levels all sstl_1.8 05 9 min. clock cycle time at cas latency = 5 -5 5 ns 50 -3.7 3.7 ns 3d -3 3 ns 30 10 sdram access time from clock at cl = 5 -5 0.6 ns 60 -3.7 0.5 ns 50 -3 0.45 ns 45 11 dimm configuration type all ecc 02 12 refresh rate/type all 7.8 s / sr 82 13 sdram width, primary all x8, x4 08 08 04 14 error checking sdram data width all x8, x4 08 08 04 15 not used all not used 00 16 burst length supported all 4 & 8 0c 17 number of sdram banks all 4 04 18 supported cas latencies all 5, 4, 3 38 19 not used all not used 00 20 dimm type information all reg. dimm 01 21 sdram module attributes all see note 1 00 22 sdram device attributes: general all incl. weak driver 01 23 min. clock cycle time at cas latency = 4 -5 5 ns 50 -3.7 3.7 ns 3d -3 3 ns 30 24 sdram access time from clock at cl = 4 -5 0.6 ns 60 -3.7 0.5 ns 50 -3 0.45 ns 45 25 min. clock cycle time at cas latency = 3 all 5 ns 50 26 sdram access time from clock at cl = 3 all 0.6 ns 60 27 minimum row precharge time (trp) -5 & -3.7 15 ns 3c -3 12 ns 30 28 minimum row act. to row act. delay (trrd) all 7.5 ns 1e 29 minimum ras to cas delay (trcd) -5 & -3.7 15 ns 3c -3 12 ns 30 30 minimum ras pulse width (tras) all 45 ns 2d 31 module density (per rank) all 40 40 80
hys72txx0xxgr registered ddr2 sdram-modules infineon technologies 19 2.04 32 address and command setup time (tis) -5 0.60 ns 60 -3.7 0.50 ns 50 -3 0.45 ns 45 33 address and command hold time (tih) -5 0.60ns 60 -3.7 0.50 ns 50 -3 0.45ns 45 34 data input setup time (tds) -5 0.40 ns 40 -3.7 0.35 ns 35 -3 0.30 ns 30 35 data input hold time (tdh) -5 0.40 ns 40 -3.7 0.35 ns 35 -3 0.30 ns 30 36 write recovery time (twr) all 15 ns 3c 37 internal write to read command delay (twtr) -5 10 ns 28 -3.7 & -3 7.5 ns 1e 38 internal read to precharge delay (trtp) all 7.5 ns 1e 39 not used not used 00 40 extension of byte 41 trc and byte 42 trfc all 00 41 minimum core cycle time (trc) -5 & -3.7 60 ns 3c -3 57 ns 39 42 min. auto refresh command cycle time (trfc) all 75 ns 4b 43 maximum clock cycle time tck all 8 ns 80 44 max. dqs-dq skew (tdqsqmax.) -5 0.35 ns 23 -3.7 0.30 ns 1e -3 0.25 ns 19 45 read data hold skew factor (tqhs) -5 0.45 ns 2d -3.7 0.40 ns 28 -3 0.35 ns 23 46 pll relock time 15.0 s 0f 47-61 reserved for ?delta temperature in spd? see note 1 00 62 spd revision revision 1.0 10 63 checksum for bytes 0 - 62 -5 7d 7e b6 -3.7 tbd. tbd. tbd. -3 tbd. tbd. tbd. 64 manufacturers jedec id code infineon c1 65-71 not used not used 00 72 module assembly location xx 73-90 module part number xx 91-92 module revision code xx 93-94 module manufacturing date year/week code xx 95-98 module serial number serial number xx 99-127 manufacturer?s specific data blank ff 128-255 open for customer use blank note 1 : will be used for future spd code revisions. for details of ?delta temperature in spd? see jedec ballot jc- 42.5 item # 1468. byte# description speed grade spd entry value hex value note: ?-5 ? := ddr2-3200 (ddr2-400) ?-3.7? := ddr2-4200 (ddr2-533) ?-3 ? := ddr2-5300 (ddr2-667) hys72t32000gr HYS72T64020GR hys72t64001gr
hys72txx0xxgr registered ddr2 sdram-modules infineon technologies 20 2.04 7.0 package outline 7.1 raw card a module package ddr2 registered dimm modules raw card a one physical rank, 9 components x8 organised note: all outline dimensions and tolerances are in accordance with the jedec standard (mo-237) detail of contacts a 2.50 0.8 1.0 0.20 + 0.05 - + 0.20 - + 0.15 - detail of contacts b 3.8 typ. 2.5 5.0 1.5 0.75r 1.27 2.7 max. + 0.1 - 133.35 65 64 63,0 120 30.0. pin 1 + 0.15 - 5.0 55,0 4.0 front view 184 185 240 17.80 3 10.0 3 pin 121 backside view 5,175 5,175 pcb warpage 0.40 pll register
hys72txx0xxgr registered ddr2 sdram-modules infineon technologies 21 2.04 7.2 raw card b module package ddr2 registered dimm modules raw card b two one physical rank, 18 components x8 organised note: all outline dimensions and tolerances are in accordance with the jedec standard (mo-237) d etail of c ontacts a 2.50 0.8 1.0 0.20 + 0.05 - + 0.20 - + 0.15 - detail of c ontacts b 3.8 typ. 2.5 5.0 1.5 0.75r 1.27 4.0 max. + 0.1 - 133.35 65 64 63,0 120 30.0. pin 1 + 0.15 - 5.0 55,0 4.0 front view 184 185 240 17.80 3 10.0 3 pin 121 backside view 5,175 5,175 pcb warpage 0.40 pll register register
hys72txx0xxgr registered ddr2 sdram-modules infineon technologies 22 2.04 7.3 raw card c module package ddr2 registered dimm modules raw card c one physical rank, 18 components x4 organised note: all outline dimensions and tolerances are in accordance with the jedec standard (mo-237) d etail of c ontacts a 2.50 0.8 1.0 0.20 + 0.05 - + 0.20 - + 0.15 - detail of c ontacts b 3.8 typ. 2.5 5.0 1.5 0.75r 1.27 4.0 max. + 0.1 - 133.35 65 64 63,0 120 30.0. pin 1 + 0.15 - 5.0 55,0 4.0 front view 184 185 240 17.80 3 10.0 3 pin 121 backside view 5,175 5,175 pcb warpage 0.40 pll register register
hys72txx0xxgr registered ddr2 sdram-modules infineon technologies 23 2.04 8.0 nomenclature (modules & components) 8.1 ddr2 dimm modules 8.2 ddr2 memory components 1 infineon prefix hys for dimm modules 7 product variations 0 = standard 2 = dual die package 2 module data width 64 = non-ecc modules 72 = ecc modules 8 package g= bga components 3 dram technology t = ddr2 9 module type r = registered dimms u = unbuffered dimms dl = small outline dimms 4 memory density per i/o 32 = 32 mb 64 = 64 mb 128 = 128 mb 256 = 256 mb 10 speed grade -5 = pc2-3200 (ddr2-400) -3.7 = pc2-4200 (ddr2-533) -3 = pc2-5300 (ddr2-667) 5 raw card generation 0 = first generation 11 die revision a = 1st generation b = 2nd generation c = 3rd generation 6 number of memory ranks 0 = one rank 2 = two ranks multiplying ?memory density per i/o? with ?module data width? and dividing by 8 for non-ecc and 9 for ecc modules gives the overall module memory density in mbytes. 1 infineon component prefix hyb for dram components 6 product variations 0 = standard 2 power supply voltage 18 = 1.8 v power supply 7 die revision a = 1st generation b = 2nd generation c = 3rd generation 3 dram technology t = ddr2 8 package type c = bga package f = bga package (lead and halogen free) 4 memory density 256 = 256 mb 512 = 512 mb 1g = 1024mb 9 speed grade -5 =...ddr2-400 -3.7 =.ddr2-533 -3 =...ddr2-667 5 memory organisation 40 = x4, 4 data in/outputs 80 = x8, 8 data in/outputs 16 = x16, 16 data in/outputs 20gr- 5-a 6 4 t 0 h y s 6 4 1 234567891011 example: 0a c - 5 1 8 t 4 0 h y b 2 5 6 1 23456789 example:

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